1. Field of the Invention
The present invention relates to a method for packaging a semiconductor chip; more particularly, the present invention relates to a method for packaging a semiconductor that generally forms larger upper portions of the leads relative to lower portions of the leads.
2. Description of the Prior Art
Microelectronic devices are typically comprised of one or more silicon die having, at least in part of, a multitude of die bond pads on a front surface, a chip body, and an interconnection scheme to connect the pads on the die to a supporting substrate and an encapsulating to ensure that the die is protected from contaminants. The combination of these elements is generally referred to as a chip package.
However, the pin count of a package such as DIP (dual inline package) according to a conventional packaging method typically is not high enough. Thus, the latest trend has been emphasized on a BGA (ball grid array) package as shown in FIG. 1, which is developed to address the need for a package of increased pin count such that the dimensions of the package are nearly identical to those of the chip being packaged therein.
Referring to FIG.1, in which a packaged semiconductor chip structure 10 of a prior art is disclosed by the Taiwanes Patent No. 348306 as a preferred embodiment. The packaged semiconductor chip structure 10 includes a chip 11 encapsulated by a molding material 12. Furthermore, a plurality of bonding pads 11a, which are electrically connected to a plurality of leads 13, are formed on the top surface of the chip 11. A conducting adhesive layer 14, which is exposed from the lower portion of the molding material 12, is adhered to the bottom surface of the chip 11 via the top. The leads 13 are exposed on the bottom surface of the molding material 12 and outside the periphery of the chip 11 for electrical connection to external circuits (not shown). Nonetheless, since the exposed leads 13 are not completely encapsulated by the molding material 12, the leads 13 can not be anchored securely by the encapsulation.
Furthermore, since only the top side of the chip 11 is completely sealed by the encapsulation of the molding material 12 and the bottom side thereof exposed, moisture and/or ionic contaminants from the immediate environment may damage the packaged semiconductor chip 10. As a result, the reliablity of the packaged semiconductor chip 10 is diminished as well as the expected life cycle of the chip 11. As the trend for the semiconductor industry is towards packaging IC devices of increasingly smaller size, it is therefore important that an IC package design capable of solving the above problems is devised.